Institute of High Performance Computing

Simulation for System-level Electronic Package (SSLEP) – An Efficient Tool for Power and Signal Integrity (PI/SI) Analysis in Advanced IC Package

Team Members:  Dr. LIU En-Xiao, Dr. WEI Xingchang, Dr. ZHANG Wenzu, and Dr. ZAW Zaw Oo
 
Contact: Dr. LI Er-Ping, Head of Computational Electronics and Photonics
Tel.: +(65) 6419 1111, Email: eplee@ihpc.a-star.edu.sg
 
SSLEP is an efficient simulation tool for the investigation of Power and Signal Integrity on ultilayer printed circuit boards (PCBs) and advanced IC packages. A broad range of methodologies integrated in SSLEP provides to identify issues such as trace and via coupling, power-ground bounce caused by simultaneous switching noise, and placement of local and global decoupling capacitors. Implemented based on equivalent microwave network method, SSLEP can simulate design structures with multilayer power-ground planes, large number of traces and up to thousands of signal and power-ground vias, efficiently in terms of CPU time and memory usage.  

 

 

Background:

The trend of continuously lowering power supply voltage level and increasing signal switching speeds in advanced IC packages and printed circuit boards challenges market-available simulation tools for signal and power integrity (PI/SI) analysis of such complex geometry structures.

             A multilayer PCB or IC package can be considered as two functions parts: signal link path and power delivery network. A signal link path consists of traces and vias to set up a communication channel between drivers and receivers; usually pins of integrated circuits (IC), while a power delivery network usually contains a stack-up of power-ground planes, a large number of power-ground vias and many decoupling capacitors to provide an extremely low impedance path from voltage regulator module (VRM) to power-ground pins of IC blocks.

            Advanced Electronics and Electromagnetics (AEE) group @ IHPC has developed a broad range of the different methodologies to model the complex structures of advanced IC packages and PCBs, and integrated into a hybrid algorithm, namely Simulation for System-level Electronic Package (SSLEP), using to investigate the PI/SI of such system. Our group has also developed a user-friendly graphic user interface (GUI) for the algorithm to perform analysis simulations.

 SSLEP Applications:

• Building up power delivery system guidelines for IC packages and boards

• Investigating PI and SI in frequency domain in 3D  
• Evaluating electromagnetic coupling within geometry structures to enable better traces and vias’ layout and decoupling capacitor placement
• Extracting frequency-dependent S, Y and Z parameters for IC package and board modeling
• Quantifying decoupling capacitor strategies and verifying placement effects
• Performing what-if analysis on potential design scenarios and stack-up options

• Easy to set up for analysis of IC packages and boards
• Quick calculation for via modeling and power-ground plate impedance  
• No meshing involved and much more efficient, in term of CPU time and memory usage, compared to the full-wave simulation methods available in market
• Ability to simulate large designs that include thousands of vias and no limit to number of layers (signal, power, ground) in both package and board structures

 Example # 1: 4-ports PCB test board, four layers, two signal vias and three power-ground vias, radii of via & anti-pad (0.25 & 0.5 mm), board dimension (75 x 50 mm), total thickness (4 mm), and substrate material (e_r: 4.1, tan d: 0.23). 

 

 

 

 

 

• Y.J. Zhang, Z. Z. Oo, X.C. Wei, E.-X. Liu, J. Fan, and E.-P. Li, "Systematic Microwave Network Analysis for Multilayer Printed Circuit Boards with Vias and Decoupling Capacitors," IEEE Trans. on Electromagnetic Compatibility, will appear in future issue, Mar 2010.
• Z. Z. Oo, E.-P. Li, X.C. Wei, E.-X. Liu, Y.J. Zhang, and L.-W. Li, "Hybridization of the scattering matrix method and modal decomposition for analysis of signal traces in a power distribution network," IEEE Trans. on Electromagnetic Compatibility, vol. 51, no. 3,pp. 784 - 791, Aug 2009.
• E.-X. Liu, E.-P. Li, Z. Z. Oo, X.C. Wei, and R. Vahldieck, "Novel methods for modeling of multiple vias in multilayered parallel-plate structures," IEEE Trans. on Microwave Theory & Techniques, vol. 57, no. 7, pp. 1724-1733, Jul 2009.
• X. C. Wei, E.-P. Li, E.-X. Liu, and R. Vahldieck, "Efficient Simulation of Power Distribution Network by Using Integral Equation and Modal Decoupling Technology," IEEE Trans. on Microwave Theory & Techniques, vol. 56, no. 10, pp. 2277-2285, Oct 2008.
• X.C. Wei, E.-P. Li, E.-X. Liu, E.-K. Chua, Z. Z. Oo, and R. Vahldieck, "Emission and susceptibility modeling of finite-size power-ground planes using a hybrid integral equation method," IEEE Trans. on Advanced Packaging, vol. 31, no. 3, pp. 536-543, Aug 2008.
• Z. Z. Oo, E.-X. Liu, E.-P. Li, X.C. Wei, Y.J. Zhang, Mark Tan, L.-W. Li, and R. Vahldieck, "A semi-analytical approach for system-level electrical modeling of electronic packages with large number of vias," IEEE Trans. on Advanced Packaging, vol. 31, no. 2, pp. 267-274, May 2008.